4位移位寄存器verilog代码
1.shiter.v
//4位移位寄存器
moduleshifter(rst,clk_in1,din,clr,dout,clk_1hz);
inputclk_in1,din,clr,rst;
output[3:0]dout;
outputclk_1hz;
reg[3:0]dout;
regclk_1hz;
wireclk,clk_test;
//calltheclk_divmodule
clk_divclk_div1(.rst(rst),.clk_in(clk_in1),.clk_out(clk),.clk_test(clk_test));
always@(posedgeclk,posedgeclr)
begin
if(clr)//clearsignal,active-highlever
begin
dout<=4'b0;
end
else
begin
dout<=dout<<1;//输出信号左移一位
dout[0]<=din;//输入信号补充到输出信号的最低位
end
end
always@(*)
begin
if(clr)
clk_1hz<=0;
else
clk_1hz<=clk_test;//outputtheclkdirectly,testwhetherthediv_freqisrightornot.
end
endmodule
2.clk_div.v
//分频器部分，获得便于试验观察的时钟信号
moduleclk_div(rst,clk_in,clk_out,clk_test);
inputrst,clk_in;
outputclk_out,clk_test;
regclk_out,clk_test;
reg[25:0]counter;//50_000_000=1011_1110_1011_1100_0010_0000_00
parametercnt=50_000_000;///50mhzisthesysclk,50_000_000=2faf080
//parametercnt=4;
always@(posedgeclk_in,negedgerst)
begin
if(!rst)
begin
clk_out<=0;
clk_test<=0;
counter<=0;
end
else
begin
counter<=counter+1;
if(counter==cnt/2-1)
begin
clk_out<=!clk_out;
clk_test<=!clk_test;//testtheclk_diviswork?
counter<=0;
end
end
end
endmodule
3.modelsim仿真模块
`timescale1ns/1ps
moduleshifter_vlg_tst();
//constants
//generalpurposeregisters
regeachvec;
//testvectorinputregisters
regclk_in1;
regclr;
regdin;
regrst;
//wires
wireclk_1hz;
wire[3:0]dout;
//assignstatements(ifany)
shifteri1(
//portmap-connectionbetweenmasterportsandsignals/registers
.clk_1hz(clk_1hz),
.clk_in1(clk_in1),
.clr(clr),
.din(din),
.dout(dout),
.rst(rst)
);
initial
begin
//codethatexecutesonlyonce
//insertcodehere-->begin
din=0;clr=0;clk_in1=0;rst=1;
#20rst=0;
#50rst=1;
#50clr=1;
#20clr=0;
#100din=1;
//#100clr=1;
//#100clr=0;
#100din=0;
#100din=1;
//-->end
$display("runningtestbench");
end
//initialforever#10clk_in1=~clk_in1;
always#10
clk_in1=~clk_in1;
always
//optionalsensitivitylist
//@(event1orevent2or....eventn)
begin
//codeexecutesforeveryeventonsensitivitylist
//insertcodehere-->begin
@eachvec;
//-->end
end
initial#10000$stop;
endmodule
